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| fully released specification - 1 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 d igital t emperature s ensor w ith i ntegrated f an c ontrol ASC7512 p roduct s pecification product description the ASC7512 has a two wire digital interface compatible with smbus 2.0. using a 10-bit ? - adc, the ASC7512 measures the temperature of a remote diode connected transistor as well as its own die. using temperature information from these two zones, an automatic fan speed control algorithm is employed to minimize acoustic impact while achieving recommended cpu temperature under vary ing operational loads. to set fan speed, the ASC7512 has a pulse width modulation (pwm) output that is controlled by one of two temperature zones. both high- and low-frequency pwm ranges are supported. the ASC7512 also includes a digital filter that can be invoked to smooth temperature readings for better control of fan speed and minimum acoustic impact. the ASC7512 has a tachometer input to measure fan speed or alternatively, an alert pin that may be triggered by exceeding a temperature limit setting. limit and status registers for all measured values are included to alert the system host that any measurements are outside of programmed limits. features ? 2-wire, smbus 2.0 compliant, serial digital interface ? 10-bit ? -adc ? monitors internal and remote thermal diodes ? programmable autonomous fan control based on temperature readings ? noise filtering of tem perature reading for fan control ? 0.25 c digital temperature sensor resolution ? pwm fan speed control output for 2-, 3- or 4-wire fans. ? provides high and low pwm frequency ranges ? fan tachometer input or alert output ? 8-lead msop or soic package measurement system temperature: ? 0.25c resolution, 1c accuracy on remote diode ? 0.25c resolution, 3c accuracy on local sensor ? extended temperature measurement range on remote sensor ?55c to +125c using or 2?s complement coding. fan tachometer: ? 16-bit count of 90khz clock periods limit alarms for all measured values applications ? desktop computers ? motherboards and graphics cards ? laptop computers ? microprocessor based equipment (e.g. base- stations, routers, atms, point of sales) connection diagram ordering information part number package temperature range and operating voltage marking how supplied ASC7512d8 8-lead soic -40c to +125c, 3.3v ASC7512 ayww 2500 units tape & reel ASC7512m8 8-lead msop -40c to +125c, 3.3v 7512 ayww 2500 units tape & reel ayww ? assembly site, year, workweek 1 2 3 4 5 6 7 8 gnd smbclk smbdat v dd d+ ASC7512 d- pwm tach / alert
- 2 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 block diagram pin descriptions symbol pin type name and function/connection smbdat 7 digital i/o (open-drain) system management bus data. open-drain output. 5v tolerant, smbus 2.0 compliant. smbus smbclk 8 digital input system management bus clock. tied to open-drain output. 5v tolerant, smbus 2.0 compliant. v dd 1 power +3.3v pin. can be powered by +3.3v standby power if monitoring in low power states is required. this pin should be bypassed with a 0.1 f capacitor in parallel with 100pf power gnd 5 ground ground for all analog and digital circuitry. d+ 2 remote thermal diode positive input positive input (current source) from the remote thermal diode serves as the positive i nput into the a/d. connected to the anode of a cpu thermal di ode or the base-collector of a diode connected mmbt3904 npn transistor. remote d- 3 remote thermal diode negative input negative input (current sink) from the remote thermal diode serves as the negative input into the a/d. connected to cathode of a cpu thermal dio de or the emitter of a diode connected mmbt3904 npn transistor. tach / alert 6 digital input / digital open-drain output input for monitoring tachometer output of fan (default) or alert output selectable by configur ation register 09h, bit 5. fan / alert pwm 4 digital open-drain output fan speed control, pulse width modulated. figure 1 block diagram tach / alert d+ d- diode signal con- ditioning & analog mux id re g isters address pointe r adc bandgap reference status re g isters fan t-min, t-ran g e & t-h y st fan control re g isters fan s p eed confi g uration smbus interface limit re g isters limit com p arators smbdat smbclk internal sensor pwm fan pwm control re g iste r fan characteristic re g isters pin mux tach signal conditione r s p ike smoothin g digital filter confi g uration re g iste r fan s p eed - 3 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 absolute maximum ratings 1 parameter rating supply voltage, v dd -0.5v to 6.0v voltage on any digital input or output pin -0.5v to 6.0v voltage on remote + -0.5v to (v dd + 0.50v) current on remote - 1ma input current on any pin 2 5ma package input current 2 20ma package dissipation at t a = 25 c see (note 3) storage temperature -65 c to +150 c human body model 2500 v esd 4 machine model 250 v operating ratings 1 parameter rating ASC7512 operating temperature range -40 c t a +125 c remote diode temperature range -55 c t d +125 c supply voltage (3.3v nominal) +3.0v to +3.6v all other inputs -0.05v to v dd + 0.05v typical supply current tbdma notes: 1. absolute maximum ratings are limits beyond which operation may cause permanent damage to the device. these are stress ratings only; functional operation at or above these limits is not implied. 2. when the input voltage (v in ) at any pin exceeds the power supplies (v in < gnd or v in > v dd ), the current at that pin should be limited to 5ma. the 20ma maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5ma to four. parasitic components and/or esd protection circuitry are present on the ASC7512 pins. care should be taken not to forward bias the parasitic diode present on pins d+ and d-. doing so by more than 50mv may corrupt temperature measurements. 3. thermal resistance junction-to-ambient when attached to a double-sided printed circuit board with 1oz. foil is tbd c/w 4. human body model: 100pf capacitor discharged through a 1.5k resistor into each pin. machine model: 200pf capacitor discharged directly into each pin. - 4 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 dc electrical characteristics 5 the following specifications apply for v dd = 3.3v, and all analog input source impedance r s = 50 ? unless otherwise specified in conditions. boldface limits apply for t a = t j over t min to 85 c ; all other limits t a = t j = 25 c. t a is the ambient temperature of the ASC7512; t j is the junction temperature of ASC7512; t d is the remote thermal diode junction temperature. specifications subject to change without notice parameter conditions min typ max units power supply characteristics converting, interface and fans inactive, peak current 1.8 3.5 ma(max) supply current converting, interface and fans inactive, average current 0.5 ma power-on reset threshold voltage 1.6 2.8 v temperature to digital converter characteristics resolution 0.25 10 c bits local sensor accuracy 6 - 40c t a +100c, 3v v dd 3.6v 1 3 c 0c t a +100c, -55c t d +125c, 3v v dd 3.6v 1 2 c remote sensor accuracy 7 -40c t a +120c, -55c t d +125c, 3v v dd 3.6v 3 c high level 96 a external diode current source i ds low level 6 a external diode current ratio 16 digital open-drain output: pwm logic low sink current i ol v ol = 0.4v 8 ma (min) logic low level v ol i out = +8ma 0.4 v (max) smbus open-drain output: smbdat logic low output voltage v ol i out = +4ma 0.4 v (max) high level output current i oh v out = v+ 0.1 10 a(max) smbus inputs: smbclk, smbdat logic input high voltage v ih 2.1 v (min) logic input low voltage v il 0.8 v (max) logic input hysteresis voltage v hyst 300 mv digital inputs: all logic input high voltage v ih 2.1 v (min) logic input low voltage v il 0.8 v (max) logic input threshold voltage v th 1.5 v logic high input current i ih v in = v+ 0.005 10 a(max) logic low input current i il v in = gnd -0.005 -10 a(max) digital input capacitance c in 20 pf - 5 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 ac electrical characteristics the following specifications apply for v dd = 3.3v unless otherwise specified in conditions. boldface limits apply for t a = t j over t min to 85 c ; all other limits t a = t j = 25 c. parameter conditions min typ max units tachometer fan full-scale count 65535 (max) fan counter clock frequency 90 khz fan count conversion time 0.7 1.46 sec(max) fan pwm output low-frequency range 10 94 hz hz frequency range high-frequency range 22.5 30 khz khz duty-cycle range 0 to 100 %(max) duty-cycle resolution (8-bits) 0.3906 %/count spin-up time interval range 0 4000 ms ms logic electrical characteristics (t a = 25 c, v dd = 3.3v unless otherwise noted) parameter symbol conditions min typ max units input voltage logic high v ih 3v v dd 3.6v 2.1 v input voltage logic low v il 3v v dd 3.6v 0.8 v output voltage logic low ( alert ) v ol v dd =5v, i ol = -6ma 0.4 v output low sink current ( alert ) i ol alert forced to 0.4v 6 ma input leakage current i in v in = 0v or 5.5v, -40c t a +125c 1.0 a smbus output sink current i ol t a = 25 c, v ol = 0.6v 6 ma smbus logic input current i ih, i il -1 +1 a output leakage current i oh v oh = v dd = 5.5v 0.1 1 a output transition time t f c l = 400pf, i ol = -3ma 250 ns input capacitance c in all digital inputs 5 pf - 6 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 serial port timing (t a = 25 c, v dd = 3.3v unless otherwise noted, guarant eed by design, not production tested) parameter symbol min typ max units scl operating frequency f scl 400 khz scl clock transition time t t:lh , t t:hl 300 ns scl clock low period t low 1.3 s scl clock high period t high 0.6 50 s bus free time between a stop and a new start condition t buf 1.3 s data in set-up to scl high t su:dat 100 ns data out stable after scl low t hd:dat 300 ns scl low set-up to sda low (repeated start condition) t su:sta 600 ns scl high hold after sda low (start condition) t hd:sta 600 ns sda high after scl high (stop condition) t su:sto 600 ns time in which ASC7512 must be operational after a power-on reset t por 500 ms 5. these specifications are guaranteed only for the test conditions listed. 6. the accuracy of the ASC7512 is guaranteed when using the t hermal diode of a processor or any thermal diode with a non-ideal ity of 1.008 and internal series resistance of 3.52 ? . when using a 2n3904 type transistor as a thermal diode the error band will be typically shifted depending on transistor characteristics. 7. accuracy (expressed in c) = difference between the ASC7512 reported output temperature and the temperature being measured. local temperature accuracy does not include the effect s of self-heating. the rise in temperature due to self-heatin g is the product of the internal power dissipation of the ASC7512 and th e thermal resistance. see (note 3) for the thermal resistan ce to be used in the self-heating calculation. 8. holding the smbdat and/or smbclk lines low for a time interval greater than t timeout will reset the ASC7512?s smbus state machine, therefore setting the smbdat pin to a high impedance state. t hd:sta t su:sto t su:dat scl sd a t buf t su:sta t hd:dat scl sda data out 10 10 90 t t:lh t t:hl t low t high 90 - 7 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 control communication smbus the ASC7512 is compatible with devices that are compliant to the smbus 2.0 specifications. more information on this bus can be found at http://www.smbus.org/ . compatibility of smbus2.0 to other buses is discussed in the smbus 2.0 specification. general operation writing to and reading from the ASC7512 registers is accomplished via the smbus-compatible two-wire serial interface. smbus protocol r equires that one device on the bus initiate and control all re ad and write operations. this device is called the ?master? device. the master device also generates the scl signal that is the clock signal for all other devices on the bus. all other devices on the bus are called ?slave? devices. the ASC7512 is a slave device. both the master and slave devices can send and receive data on the bus. during smbus operations, one data bit is transmitted per clock cycle. all smbus operations follow a repeating nine clock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ack) or not acknowledge (nack) from the receiving device. note that there are no unused clock cycles during any operation? therefore there must be no br eaks in the stream of data and acks / nacks during data transfers. for most operations, smbus protocol requires the sda line to remain stable (unmoving) whenever scl is high ? i.e. any transitions on the sda line can only occur when scl is low. the exceptions to this rule are when the master device issues a start or stop conditi on. note that the slave device cannot issue a start or stop condition. smbus definitions the following are definitions for some general smbus terms: start condition: this condition occurs when the sda line transitions from high to low while scl is high. the master device uses this condition to i ndicate that a data transfer is about to begin. stop condition: this condition occurs when the sda line transitions from low to high wh ile scl is high. the master device uses this condition to signal the end of a data transfer. acknowledge and not acknowledge: when data are transferred to the slave device it sends an ?acknowledge? (ack) after receiving each byte. the receiving device sends an ack by pulling sda low for one clock. following the last byte, a master device sends a "not acknowledge" (nack) followed by a stop condition. a nack is indicated by forcing sda high during the clock after the last byte. slave address ASC7512 is designed to be used primarily in desktop systems that require only one monitoring device. the smbus slave address is fixed at 58 hex (x 1 0 1 1 0 0 0 binary). writing to and reading from the ASC7512 all read and write operations must begin with a start condition generated by the mast er device. after the start condition, the master devic e must immediately send a slave address (7-bits) followed by a r/ w bit. if the slave address matches the address of the ASC7512, it sends an ack by pulling the sda line low for one clock. read or write operations may contain one- or two-bytes. see figures 2 through 6 for timing diagrams for all ASC7512 operations. setting the register address pointer for all operations, the address pointer stored in the address pointer register must be pointing to the register address that is going to be written to or read from. this register?s content is automatically set to the value of the first byte following the r/ w bit being set to 0. after the ASC7512 sends an ack in response to receiving the address and r/ w bit, the master device must transmit an appropriate 8-bit address pointer value as explained in the registers section of this data sheet. the ASC7512 will send an ack after receiving the new pointer data. the register address pointer set operation is illustrated in figure 2. if the address pointer is not a valid address the ASC7512 will internally terminate the operation. also recall that the address register reta ins the current address pointer value between operations. ther efore, once a register is being pointed to, subsequent read operations do not require another address pointer set cycle. writing to registers all writes must start with a pointer set as described previously, even if the pointer is already pointing to the desired register. the sequence is described in figure 2. immediately following the pointer set, the master must begin transmitting the data to be written. after transmitting each byte of data, the master must release the sda line for one clock to allow the ASC7512 to acknowledge receiving the byte. the write operation should be terminated by a stop condition from the master. reading from registers to read from a register other than the one currently being pointed to by the address pointer register, a pointer set sequence to the desired register must be done as described previously. immediately following the pointer - 8 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 set, the master must perform a repeat start condition that indicates to the ASC7512 that a read is about to occur. it is important to note that if the repeat start condition does not occur, the ASC7512 will assume that a write is taking place, and the selected register will be overwritten by the upcoming data on the data bus. the read sequence is described in figure 4. after the start condition, the master must again send the device address and read/write bit. this time the r/ w bit must be set to 1 to indicate a read. the rest of the read cycle is the same as described in the previous paragraph for reading from a preset pointer location. if the pointer is already pointing to the desired register, the master can read from that register by setting the r/ w bit (following the slave address) to a 1. after sending an ack, the ASC7512 will begin transmitting data during the following clock cycle. after receiving the 8 data bits, the master device should respond with a nack followed by a stop condition. if the master is reset while the ASC7512 is in the process of being read, the master should perform an smbus reset. this is done by holding the data or clock low for more than 35ms, allowing all smbus devices to be reset. this follows the smbus 2.0 specif ication of 25-35ms. when the ASC7512 detects an smbus reset, it will prepare to accept a new start sequence and resume communication from a known state. 1 a7 a6 a5 a4 a3 a2 a1 a0 start smbus device address byte (58h) register address byte a a ack from ASC7512 ack from ASC7512 scl sda 1 0 0 1 s 0 0 1 9 1 9 a7 a6 a5 a4 a3 a2 a1 a0 start smbus device address byte (58h) register address byte r/w a a ack from ASC7512 ack from ASC7512 scl 1 9 1 9 stop by master 1 9 d7 d6 d5 d4 d3 d2 d1 d0 register data byte a ack from ASC7512 stop by master r/w 1 0 0 1 s 0 0 sda 1 d7 d6 d5 d4 d3 d2 d1 d0 re-start register data byte a n r/w smbus device address byte (58h) ack from ASC7512 nack from master stop by master register address pointer set (figure 2.) without stop by master + 1 9 1 9 1 0 0 1 s 0 0 1 figure 2 register address pointer set figure 3 register write figure 4 register read - 9 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 1 s 0 1 1 0 smbus device address byte (58h) ack from ASC7512 nack from master scl sda 1 9 1 9 stop by master d7 d6 d5 d4 d3 d2 d1 d0 start 0 register data byte a n 0 r/w figure 5 register read when read address already set s 0 1 0 1 1 0 0 0 1 start 0 smbus alert response address byte (0ch) ASC7512 smbus address 1 1 0 0 a n ack from ASC7512 nack from master scl sda 0 1 9 1 9 stop by master figure 6 smbus alert response r/w - 10 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 operation a lert output the ASC7512 has an emergency alarm function, alert that is optionally assigned to pin 6, the tach / alert pin. alert is determined by both high and low limits and will also respond to a remote diode open circuit failure. these limits are settable separately for zone 1 and zone 2 sensors. any alarm condition is reported individually in the status register and may be read at any time on the smbus. alarm conditions are logically combined and used to drive an open-drain output, the alert output, (pin 6). this output pin may be used as an interrupt signal the cpu or to turn on remote drivers for fans or indicators. the alert pin will remain asserted until it has been reset by the host via the smbus. a lert limits figure 7 shows use of the alert high and low limits. the user sets up the alarm by writing the upper and lower limit temperatures into the lim it registers over the smbus. after each measurement, the comparator tests the readings against the programmed limits and if the measurement exceeds the high lim it is or is equal to or less-than the low limit, it will assert the particular alarm bits in the status register and cause the alert pin to go low. figure 7 a lert limits and responses the status bits will remain hi gh until the status register is read and then, if the conditio n is no longer present those bits will be reset, otherwise they will remain high until the conditions are no longer met and the register is read again. the same sequence applies to the local readings and limits. the alert pin will remain low until the status bits have been reset and an alert response has been issued by the master and responded by the ASC7512. this flow is described below. the user may mask-out or disable the alert signal pin should it be necessary to prevent a processor interrupt. this is controlled by setting bit 7 of the configuration register. smbus alert output the alert pin may be used to signal an smbus alert to the host processor. this is a special mode of the smbus interface that requires the smbus host to send an alert response address (ara) to all slaves sharing the alert pin in order to isolate clear and service the alerting device. this sequence is described below and in figure 6. the sequence of servicing this interrupt is as follows: 1. alert is asserted by the ASC7512 driving pin 6 low. 2. the smbus master begins a read operation with a start followed by the ara response address, 0001 100. this is an smbus general call address to be used only for requesting an alert response. 3. the device providing the alert signal responds to this by providing an ack followed by its own bus address, an ASC7512 will provide, 101 1000, with the lsb of the data byte set to 1. a nack response is expected from all devices not giving an alert . 4. if more than one device responds, the device with the lowest device address will have priority and will be serviced first by the master. 5. the service routine must read the status register of the alerting device to determine the nature of the alert. if the alerting condition is still present, the status bit will remain set, continuing to activate the alert pin. if the condition is removed, the status bit will be cleared and an additional ara will now de-assert the alert pin. zn1 low alert limit temperature conversion zn1 high alert limit status bit-4, rhigh status bit-3, rlow status register read ara response alert pin 6 - 11 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 register set register address r/w register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) de- fault value (hex) lock 02h r alert status busy lhigh llow rhigh rlow ropen x x 00 09h r/w configuration alert mask run/ stop alert/ tach res res res res res 00 0ah r/w conversion rate conv7 conv6 conv5 conv4 conv3 conv2 conv1 conv0 08 0bh r/w zone 2 high alert limit 7 6 5 4 3 2 1 0 55 0ch r/w zone 2 low alert limit 7 6 5 4 3 2 1 0 00 0dh r/w zone 1 high alert limit (ms byte) 9 8 7 6 5 4 3 2 55 0eh r/w zone 1 low alert limit (ms byte) 9 8 7 6 5 4 3 2 00 0fh r/w one shot measurement res res res res res res res res 00 10h r zone 1 temperature (ls byte) 1 0 x x x x x x 00 11h r/w zone 1 offset (ms byte) 9 8 7 6 5 4 3 2 00 12h r/w zone 1 offset (ls byte) 1 0 res res res res res res 00 13h r/w zone 1 high alert limit (ls byte) 1 0 x x x x x x 00 14h r/w zone 1 low alert limit (ls byte) 1 0 x x x x x x 00 15h r zone 2 temperature (ls byte) 1 0 x x x x x x 00 22h r/w consecutive alert smb time- out res res res consec alert 3 consec alert 2 consec alert 1 consec alert 0 01 25h r zone 1 temperature 9 8 7 6 5 4 3 2 00 26h r zone 2 temperature 9 8 7 6 5 4 3 2 00 28h r tach lsb 7 6 5 4 3 2 1 0 00 29h r tach msb 15 14 13 12 11 10 9 8 00 30h r/w fan current pwm duty 7 6 5 4 3 2 1 0 ff 3ah r/w tach configuration tach1 disable 3-wire enable meas blank1 meas blank 0 meas dwell 1 meas dwell 0 meas duration 1 meas duration 0 36 3eh r company id 7 6 5 4 3 2 1 0 61 3fh r version/ stepping ver3 ver2 ver1 ver0 stp3 stp2 stp1 stp0 62 40h r/w ready/lock/ start/override res res res res ovrid ready lock start 00 - 12 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 register address r/w register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) de- fault value (hex) lock 41h r interrupt status register 1 err res zn2 zn1 res res res res 00 42h r interrupt status register 2 res err1 res res res fan res res 00 4eh r/w zone 1 low temperature 7 6 5 4 3 2 1 0 81 4fh r/w zone 1 high temperature 7 6 5 4 3 2 1 0 7f 50h r/w zone 2 low temperature 7 6 5 4 3 2 1 0 81 51h r/w zone 2 high temperature 7 6 5 4 3 2 1 0 7f 54h r/w tach minimum lsb 7 6 5 4 3 2 1 0 ff x 55h r/w tach minimum msb 15 14 13 12 11 10 9 8 ff x 5ch r/w fan configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62 x 5fh r/w fan range/ frequency ran3 ran2 ran1 ran0 hlfrq frq2 frq1 frq0 c3 x 60h r/w zone 2 range ran3 ran2 ran1 ran0 res res res res c3 x 62h r/w min/off, zone1 spike smoothing res res off1 res zn1e zn1-2 zn1-1 zn1-0 00 x 63h r/w zone2 spike smoothing zn2e zn2-2 zn2-1 zn2-0 res res res res 00 x 64h r/w fan pwm minimum 7 6 5 4 3 2 1 0 80 x 67h r/w zone1 fan temp limit 7 6 5 4 3 2 1 0 5a x 68h r/w zone 2 fan temp limit 7 6 5 4 3 2 1 0 5a x 6ah r/w zone 1 temp absolute limit 7 6 5 4 3 2 1 0 64 x 6bh r/w zone 2 temp absolute limit 7 6 5 4 3 2 1 0 64 x 6dh r/w zone 1, zone 2 hysteresis h1-3 h1-2 h1-1 h1-0 h2-3 h2-2 h2-1 h2-0 44 x 75h r/w fan spin-up mode res res res res res res res pwm1su 07 x note: reserved bits will always return 0 when read, x-bits in readings are to be ignored. - 13 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 temperature measurement temperatures are measured with a precision delta-v be methodology converted to a digita l temperature reading by a 10-bit sigma-delta converter. the user may set limits on these readings to be continuously monitored and alarm bits set when they are exceeded. separately, the measurements are also delivered to the automatic fan c ontrol system to adjust fan speed. the following registers contain the readings fr om the internal and remote sensors. registers 25-10h and 26-15h: zone temperature reading (10-bit, 2?s complement reporting) register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 25h r zone 1 temperature 9 8 7 6 5 4 3 2 00 10h r zone 1 temperature (ls byte) 1 0 x x x x x x 00 26h r zone 2 temperature 9 8 7 6 5 4 3 2 00 15h r zone 2 temperature (ls byte) 1 0 x x x x x x 00 the zone temperature registers reflect t he current temperature of the internal and remote diodes. processor (zone 1) temp register reports the temperature measured by the thermal diode connected to the remote - and remote + pins. internal (zone 2) temp register reports the temperature measured by the internal (junction) temperature sensor. temperatures are represented as 10 bit, 2?s complem ent, signed numbers, in celsius, as shown below in table 1. the temperature reading register will return a value of 8000h if the remote diode pins are not used by the board designer or are not functioning properly. this reading will cause the zone limit bit (bit 4) in t he interrupt status register (41h) and th e remote diode fault status bit (bit 6) in the interrupt status register 2 (42h) to be set. these registers are read-only ? a wri te to these registers has no effect. digital output (2?s complement) high byte low byte temperature 10-bit resolution ignore +125 c 0111 1101 00 xx xxxx +100 c 0110 0100 00 xx xxxx +50 c 0011 0010 00 xx xxxx +25 c 0001 1001 00 xx xxxx +10 c 0000 1010 00 xx xxxx +1.75 c 0000 0001 11 xx xxxx +0.25 c 0000 0000 01 xx xxxx 0 c 0000 0000 00 xx xxxx -1.75 c 1111 1110 01 xx xxxx -55 c 1100 1001 00 xx xxxx table 1 relationship between temperature and 2?s complement digital output, -55c to +125c temperature measurement conf iguration and alert limits registers 09h, 0ah, 0fh, 22h: conversion rate and alert configuration register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 09h r/w configuration alert mask run/ stop alert/ tach res res res res res 00 0ah r/w conversion rate conv7 conv6 conv5 conv4 conv3 conv2 conv1 conv0 08 - 14 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 0fh r/w one shot measurement res res res res res res res res 00 22h r/w consecutive alert smb time- out res res res consec alert 3 consec alert 2 consec alert 1 consec alert 0 01 these configuration register settings apply to measur ements and alerts reported in registers 25h-10h and 26h-15h temperature readings (10-bit 2?s complement reporting). one-shot measurement register address 0fh initiates a temperature measurement when ASC7512 is in stop mode and returns to that m ode after both temperature measurements are complete. bit name r/w default description 0:3 reserved r/w 0 reserved 5 alert/tach r/w 0 selection between tach input and alert output for pin 6, default is tach input. 6 run/stop r/w 0 measurement system run(default) or stop, places ASC7512 in a low-powe r or sta ndby mode. 7 alert mask r/w 0 mask alarm conditions from asserting alert pin 6 when alert function of pin 6 is enabled. table 2 configuration register [09h] bits bit name r/w default description 3:0 conversion rate r/w 08h temperature measurement rate for a set of internal and external readings. conversions per second seconds per conversion code (hex) 0.0625 16 00 0.125 8 01 0.25 4 02 0.5 2 03 1 1 04 2 0.5 05 4 0.25 06 5 0.2 d0 8 0.125 07 16 (default) 0.0625 08 32 0.03125 09 64 0.015625 0a table 3 conversion rate register [0ah] bits - 15 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 bit name r/w default description 3:0 consecutive alert r/w 000 the number of consecutive out-of-limit measurements required to set the alert pin. 1: 000 2: 001 3: 011 4: 111 6 reserved r/w 0 reserved 7 smbtimeout r/w 0 enables a reset of the ASC7512 smbus interface if it detects smbus clock stuck low for more than 35 milli- seconds. table 4 consecutive alert register [22h] bits register 0b-0eh and 11-14h: alert temperature limits (compared to registers 25h-14h, 26h-15h) register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 0bh r/w zone 2 high alert limit 7 6 5 4 3 2 1 0 55 0ch r/w zone 2 low alert limit 7 6 5 4 3 2 1 0 00 0dh r/w zone 1 high alert limit (ms byte) 9 8 7 6 5 4 3 2 55 13h r/w zone 1 high alert limit (ls byte) 1 0 x x x x x x 00 0eh r/w zone 1 low alert limit (ms byte) 9 8 7 6 5 4 3 2 55 14h r/w zone 1 low alert limit (ls byte) 1 0 x x x x x x 00 these limits are compared zone 1 and zone 2 registers and trigger the optional alert signal pin and status bits that may be enabled in register 09h, bit-5. the limits are in binary te mperature format representing values from 0 to +127 degrees. status registers register 02h: alert status register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 02h r alert status busy lhigh llo w rhigh rlow ropen res res 00 the alert status register is a read-only re gister for reporting the stat e of the ASC7512?s alarms. it is a read-only register located at 02h. when any high or low zone 1 (remote) limits or high or low zone 2 (local) limits are exceeded, bits 3 through 6 are set accordingly and the alert pin 6 will be driven low. if the remote sensor is open-circuit, bit 2 will be set and the alert will be asserted. reading the status register will re-set these flags if the alerted condition has been removed, however, the alert pin will remain asserted until the ma ster has serviced the smbus alert. this register is read-only ? a write to this register has no effect. - 16 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 bit name r/w default description 1:0 reserved r 0 reserved 2 ropen r 0 zone 1 (remote) sensor open-circuit 3 rlow r 0 zone 1 (remote) sensor low limit 4 rhigh r 0 zone 1 (remote) sensor > high limit 5 llow r 0 zone 2 (local) sensor low limit 6 lhigh r 0 zone 2 (local) sensor > high limit 7 busy r 0 converter in process of conversion table 5 alert status register register 41h: interrupt status register 1 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 41h r interrupt status 1 err res zn2 zn1 res res res res 00 the interrupt status register 1 bits will be automatically set, by the ASC7512, whenever a fault condition is detected. a faul t condition is detected whenever a measured value is outside the window set by its limit registers. zn1 bit will be set when a diode fault condition, such as an open or short, is detected. more than one fault may be indicated in the interrupt register when read. the register will hold a set bi t(s) until the event is read by software. t he contents of this register will be cle ared (set to 0) automatically by the ASC7512 after it is read by so ftware, if the fault condition no longer exists. once set, the interrupt status register 1 bits will remain set until a read event occurs, even if the fault condition no longer exists. this register is read-only ? a write to this register has no effect. bit name r/w default description 3:0 res r 0 reserved 4 zone 1 limit exceeded r 0 the ASC7512 automatically sets this bit to 1 when the temperature input measured by the remote1- and remote1+ inputs is less than or equal to the limit set in the processor (zone 1) low temp register or more than the limit set in the processor (zone 1) high temp register. this bit will be set when a diode fault is detected. 5 zone 2 limit exceeded r 0 the ASC7512 automatically sets this bit to 1 when the temperature input measured by the internal temperature s ensor is less than or equal to the limit set in the thermal (zone2) low temp register or greater than the limit set in the internal (zone2) high temp register. 6 res r 0 reserved 7 error in status register 2 r 0 if there is a set bit in status register 2, this bit will be set to 1. table 6 interrupt status register 1 register 42h: interrupt status register 2 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 42h r interrupt status 2 res err1 res res res fan res res 00 the interrupt status register 2 bits will be automatically se t, by the ASC7512, whenever a fault condition is detected. interrupt status register 2 identifies faults caused by temper ature sensor error, fan speed dropping below minimum set by the tachometer minimum register. interrupt status register 2 will hold a set bit until the event is read by software. the contents of this register will be cleared (set to 0) automatically by the ASC7512 afte r it is read by software, if fault condit ion no longer exists. once set, the interrupt status register 2 bi ts will remain set until a read event occurs, even if the fault no longer exists. this register is read-only ? a write to this register has no effect. - 17 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 bit name r/w default description 0:1 res r 0 reserved 2 fan stalled r 0 the ASC7512 automatically sets this bit to 1 when the tach1 input reading is above the count value set in the tach1 minimum msb and lsb registers. 5:3 res r 0 reserved 6 remote diode fault r 0 the ASC7512 automatically sets this bit to 1 when there is an open circuit fault on the remote1+ or remote1- thermal diode input pins. a diode fault will also set bit 4 diode 1 zone limit bit, of interrupt status register 1. 7 res r 0 reserved table 7 interrupt status register 2 tachometer measurement and configuration register 28-29h: fan tachometer reading register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 28h 29h r r tach lsb tach msb 7 15 6 14 5 13 4 12 3 11 2 10 1 9 0 8 n/a n/a the fan tachometer reading register s contains the number of 11.111 s periods (90 khz) between full fan revolutions. the results are based on the time interval of two tachometer pul ses, since most fans produce two tachometer pulses per full revolution. these registers will be updated at least once every second. the value, for each fan, is repres ented by a 16-bit unsigned number. the fan tachometer reading registers will always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional, however, if pwm command (register 30h) is zero, tach measurements are suspended and the last reading may remain in the register. ff ffh indicates that the fan is not spinning, or that the tachometer input is not c onnected to a valid signal. these register s are read-only ? a write to these registers has no effect. when the lsbyte of the ASC7512 16-bit regist er is read, the other byte (msbyte) is latched at the current value until it is read. at the end of the msbyte read t he fan tachometer reading registers are updated. during spin-up, the pwm duty cycle reported is 0%. register 3ah: fan tachometer measurement configuration register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3ah r/w tach1 configuration tach1 disable 3-wire enable meas blank 1 meas blank 0 meas dwell 1 meas dwell 0 meas duration 1 meas duration 0 36 the fan tachometer configurati on registers contain the settings that define the modes of measurement of the tachometer input signal. the user is allowed to disable a tachometer measur ement or to request pwm stretching, in the case of a 3-wire fan. also, the rate, start-up and period of measurements within a fan rotation cycle may be selected. the table below describes the controls. - 18 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 bit name r/w default description 1:0 measurement duration r/w 10 the amount of fan rotation used for the tach measurement. assumes 2 pulse periods per rotation of fan. 00: ? rotation ? tach count x4 = reported value 01: ? rotation ? tach count x2 = reported value 10: 1 rotation ? tach count x1 = reported value (default) 11: 2 rotation ? tach count x1 = reported value 3:2 measurement dwell r/w 01 delay between tach measurements 00: 100 ms 01: 300 ms (default) 10: 500 ms 11: 728 ms 5:4 measurement blank r/w 11 in 3-wire fan mode, a delay is needed to assure that the tach input has stabilized after the pwm has been set to 100% 00: 11.1 s 01: 22.2 s 10: 33.3 s 11: 44.4 s (default) 6 3-wire enable r/w 0 when high, forces the pwm to stay high for the duration of a tach measurement for a 3-wire fan. this will result in increasing the pwm on-time percentage vs. the value in the pwm register. 7 tach disable r/w 0 suspends the 90kh z clock for power savings when high. table 8 tachometer configuration register - 19 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 automatic fan control auto fan control operating mode the ASC7512 includes the circuitry for automatic fan control. in auto fan mode, the asc75 12 will automatically adjust the pwm duty cycle of the pwm output. pwm outputs are assigned to a thermal zone based on the fan configuration registers. at any time, the temperature of a zone exceeds its absolute limit, all pwm outputs will go to 100% duty cycle to provide maximum cooling to the system. figure 8 automatic fan speed control example example for pwm1 assigned to zone 1: ? zone 1 fan temp limit (register 67h) is set to 50 c (32h). ? zone 1 range (register 5fh) is set to 8 c (6xh). ? fan pwm minimum (register 64h) is set to 50% (32h). in this case, the pwm duty cycle will be 50% at 50 c. since (zone 1 fan temp limit) + (zone 1 range) = 50 c + 8 c = 58 c, the fan will run at 100% duty cycle when the temperature of the z one 1 sensor reaches 58 c. since the midpoint of t he fan control range is 54 c, and the median duty cycle is 75% (halfway between the pwm minimum and 100%), pwm1 duty cycle would be 75% at 54 c. above (zone 1 fan temp limit) + (zone 1 range), the duty cycle will be 100%. 5 c hysteresis temperature c pwm set to off or minimum below this temperature pwm 100% fan temp limit less hysteresis fan temp limit hysteresis (0 c to 15 c) range (2 c to 80 c) fan temp limit plus range absolute limit p w m d u t y c y c l e l i n e a r l y i n c r e a s i n g w i t h t e m p p w m du t y c y c l e l i n e a r l y d e c r e a s i n g w i t h t e m p pwm set to off example 45 58 80 min% 100% pwm % minimum pwm set to 50%, fan speed increases linearly beyond 50 c but will not return to off until it has gone below fan temp limit by the 5 c hysteresis setting to 45c. temperature pwm % linear control range 8 c range off/ min% pwm set to minimum 100% 0% 50 user choice: set to minimum or off 5 c hysteresis temperature c pwm set to off or minimum below this temperature pwm 100% fan temp limit less hysteresis fan temp limit hysteresis (0 c to 15 c) range (2 c to 80 c) fan temp limit plus range absolute limit p w m d u t y c y c l e l i n e a r l y i n c r e a s i n g w i t h t e m p p w m du t y c y c l e l i n e a r l y d e c r e a s i n g w i t h t e m p pwm set to off example 45 58 80 min% 100% pwm % minimum pwm set to 50%, fan speed increases linearly beyond 50 c but will not return to off until it has gone below fan temp limit by the 5 c hysteresis setting to 45c. temperature pwm % linear control range 8 c range off/ min% pwm set to minimum 100% 0% 50 user choice: set to minimum or off - 20 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 figure 9 automatic fan control algorithm fan register device set-up the bios will follow the following steps to configure the fan registers on the ASC7512. t he registers corresponding to each function are listed. all steps may not be nec essary if default values are acceptable. regardless of all changes made by the bios to the fan limit and parameter regi sters during configuration, the ASC7512 will continue to operate based on default values until the start bit (bit 0), in the ready/lock/start/ove rride register (address 40h), is set. once the fan mode is updated, by setting the start bit to 1, the ASC7512 will operate using the values that were set by the bios in the fan control limit and parameter registers (a ddress in the range 5ch through 6dh). 1. set limits and parameters (not necessarily in this order): ? [5f-60h] set pwm frequency for the fan and auto fan control range for each zone. ? [62-63h] set spik e smoothing and min/off. ? [5ch] set the fan spin-up delay. ? [75h] set pwm spin-up mode to terminate after time set in [5ch]. value = 00h instead of default 01h. ? [5ch] match fan with a corresponding thermal zone. ? [67-68h] set the f an temperature limits. ? [6a-6bh] set the tem perature absolute limits. ? [64h] set the pwm minimum duty cycle. ? [6dh] set the temperature hysteresis values. 2. [40h] set bit 0 (start) to update f an control and limit register values an d start fan control based on these new values. [40h] (optional) set bit 1 (lock) to lo ck the fan limit and parameter registers. warning: this is a non-reversible change in state and locks out further change in critical fan control parameters until power is removed from the ASC7512. begin fan spin up set fan output to 100% end polling cycle begin polling cycle fan output at 0%? fan spinning up? set fan output to auto fan mode minimum speed set fan output to 0% temp >= abslimit? temp >= limit? fan output at 0%? off / min set to 1? temp >= hysteresis? override pwm output to 100% set fan speed based on auto fan range algorithm auto fan mode initiated yes yes (minimum speed) yes yes yes yes yes no no no no no no no no (off) yes min speed or spin-up time met? end fan spin up - 21 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 register 5f-60h: auto fan speed range, pwm frequency register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 5fh r/w zone 1 range fan1 frequency ran3 ran2 ran1 ran0 hlfrq frq2 frq1 frq0 c3 x 60h r/w zone 2 range ran3 ran2 ran1 ran0 res res res res c3 x in auto fan mode, when the temperature for a zone is a bove the temperature limit (registers 67-69h) and below its absolute temperature limit (registers 6a-6bh), the speed of a fan assigned to that zone is determined as follows: when the temperature reaches the fan temp limit for a zone, the pwm output assigned to that zone will be fan pwm minimum. between fan temp limit and (fan temp limit + range), the pwm duty cycle will increase linearly according to the temperature as shown in the figure below. the pwm duty cycle will be 100% at (fan temp limit + range). pwm frequency - frq[3:0] and hlfrq the pwm frequency bits [3:0] determine the pwm frequency for t he fan. the ASC7512 has high and low frequency ranges for the pwm outputs that are controlled by the hlfrq bit. pwm frequency selection (default = 0011 = 30.04 hz). hlfrq frq [2:0] pwm frequency 0 000 10.01 hz 0 001 15.02 hz 0 010 23.14 hz 0 011 30.04 hz (default) 0 100 38.16 hz 0 101 47.06 hz 0 110 61.38 hz 0 111 94.12 hz 1 000 22.5 khz 1 001 24 khz 1 010 25.7 khz 1 011 25.7 khz 1 100 27.7 khz 1 101 27.7 khz 1 110 30 khz 1 111 30 khz table 9 register setting vs pwm frequency ran[3:0] linear control range ( c) 0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 - 22 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 ran[3:0] linear control range ( c) 1010 20 1011 26.67 1100 32 (default) 1101 40 1110 53.33 1111 80 table 10 zone range setting, ran[3:0] this register becomes read-only when the ready/lock/start/overri de register lock bit is set. an y further attempts to write to this register shall have no effect. after power up the default value is used whenever the ready/lock/start/override register start bit is cleared even though modi fications to this register are possible. register 40h: ready/lock/start/override register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 40h r/w ready/lock/start/ override res res res res ovrid ready lock start 00 bit name r/w default description 0 start r/w 0 when software writes a 1 to this bi t, the ASC7512 fan monitoring and pwm output control functions will use the va lues set in the fan control limit and parameter registers (address 5ch through 6eh). before this bit is set, the ASC7512 will not update the used register values, the default values will remain in effect. whenever this bit is set to 0, the ASC7512 fan monitoring and pwm output control functions use the default fan limits and parameters, regardless of the current values in the limit and parameter registers (5c through 6e). the ASC7512 will preserve the values currently stored in the limit and parameter registers when this bi t set or cleared. this bit is not affected by the state of the lock bit. it is expected that all limit and parameter registers will be set by bios or application software prior to setting this bit. 1 lock r/w 0 setting this bit to 1 locks specified limit and parameter registers. warning: once this bit is set, limit and parameter registers become read-only and will remain locked until the device is powered off . this register bit becomes read-only once it is set. 2 ready r 0 the ASC7512 sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all a/d converters are properly functioning. 3 ovrid r/w 0 if this bit is set to 1, all pwm output s will go to 100% duty cycle regardless of whether or not the lock bit is set. the ovrid bit has precedence over the disabled mode. therefore, when ovrid is set the pwm will go to 100% even if the pwm is in the disabled mode. 4-7 reserved r 0 reserved table 11 ready / lock / start / ovrid settings register 30h: current pwm duty cycle register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 30h r/w fan current pwm duty 7 6 5 4 3 2 1 0 n/a - 23 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 the current pwm duty registers store t he current duty cycle at each pwm output. at initial power-on, the pwm duty cycle is 100% and thus, when read, this register will return ffh. a fter the ready/lock/start/override r egister start bit is set, thi s register and the pwm signals will be updated based on the algor ithm described in the auto fan control operating mode section. when read, the current pwm duty registers return the current pwm duty cycle. these registers are read-only unless the fan is in manual (test) mode, in which case a write to these registers will directly control the pwm duty cycle for each fan. the pwm duty cycle is represented as shown in table 12. if a 3-wire fan is being used and the option to enable 3-wire ta ch measurement is selected, the effective pwm duty cycle will be impacted by this feature. the 3-wire enable setting will hold the pwm signal high for the period taken to make a tachometer reading. this period depends on the rpm and various tachometer meas urement parameters. overall impact is that lower pwm commands will be effectively increased and there may be acoustic effects. register value current pwm % binary hex 0% 0000 0000 00 ~25% 0100 0000 40 ~50% (default) 1000 0000 80 ~75% 1100 0000 c0 100% 1111 1111 ff table 12 current pwm duty cycle setting register 4e-51h: thermal zone temperature limit registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 4eh r/w zone 1 low temp 7 6 5 4 3 2 1 0 81 4fh r/w zone 1 high temp 7 6 5 4 3 2 1 0 7f 50h r/w zone 2 low temp 7 6 5 4 3 2 1 0 81 51h r/w zone 2 high temp 7 6 5 4 3 2 1 0 7f if an external temperature input or the internal temperature sensor either exceeds the value set in the corresponding high limit register or falls below the value set in the corresponding low limit register, the corresponding bit will be set automati cally by the ASC7512 in the interrupt status register 1 (41h). for example, if the temperatur e read from the remote - and remote + inputs exceeds the zone 1 high temp register limit setting, interrupt status register 1 zn1 bit will be set. the temperature limits in these registers ar e represented as 8 bit 2?s complement, signed numbers in celsius, as shown below in table 13. setting the ready/lock/st art/override register lock bit has no effect on these registers. temperature temperature limit (2?s complement) >127 c 0111 1111 +127 c (default high) 0111 1111 +125 c 0111 1101 +90 c 0101 1010 +50 c 0011 0010 +25 c 0001 1001 0 c 0000 0000 -50 c 1100 1110 -127 c (default low) 1000 0001 table 13 zone temperature high- and low-limit registers - 8-bit two?s complement - 24 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 register 54-55h: fan tachometer minimum limits register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 54h 55h r/w tach minimum lsb tach minimum msb 7 15 6 14 5 13 4 12 3 11 2 10 1 9 0 8 ff ff the fan tachometer low limit registers indicate the tachomet er reading under which the corresponding bit will be set in the interrupt status register 2 register. in auto fan control m ode, the fan can run at low speeds, so care should be taken in software to ensure that the limit is high enough not to cause sporadic alerts. the fan tachometer will not cause a bit to be set in interrupt status register 2 if the current value in current pwm duty registers is 00h or if the fan 1 disabled via the f an configuration register. interrupts will never be gener ated for a fan if its minimum is set to ff ffh. given the relative insignificance of bit 0 and bit 1 of tach minimum lsb, these bits could be programmed to designate the physical location of the fan generati ng the tachometer signal, as follows: register name bit 1 bit 0 (lsb) cpu cooler 0 0 memory controller 0 1 chassis front 1 0 chassis rear 1 1 table 14 fan location setting the ready/lock/start/ove rride register lock bit has no effect on these registers. register 5ch: fan thermal zone assignment and spin-up mode register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 5ch r/w fan configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62 x this register becomes read-only when the ready/lock/start/override register lock bi t is set. any further attempts to write to this register shall have no effect. after power up the default value is used whenever the ready/lock/start/override register start bit is cleared even though modi fications to this register are possible. bits [7:5] zone/mode bits [7:5] of the fan configuration registers associate each fan with a temperature sensor. when in auto fan mode the fan will be assigned to a zone, and its pwm duty cycle will be adjust ed according to the temperature of that zone. if ?hottest? option is selected (110), the fan will be c ontrolled by the the hotter of zones 1, or 2. to determine the ?hotter zone?, the pwm level for each zone is calculated then the zone with the hi gher pwm value (not temperature) is selected. when in manual control mode, the current pwm dut y register (30h) become read/write. it is then possible to control the pwm outputs with software by writing to these registers. when t he fan is disabled (100) the corresponding pwm output should be driven low (or high, if inverted). zone 1: external diode (processor) zone 2: internal sensor - 25 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 fan configuration zon[2:0] fan on zone 1 auto 000 fan on zone 2 auto 001 reserved 010 fan always on full 011 fan disabled 100 fan on zone 2 auto 101 fan controlled by hotter of zones 1 or 2 110 fan manually controlled (test mode) 111 table 15 fan zone setting bit [4] pwm invert bit [4] inverts the pwm output. if set to 0, 100% duty cycle will yield an output that is always high. if set to 1, 100% duty cycle will yield an output that is always low. bit [3] reserved bit [2:0] spin up bits [2:0] specify the ?spin up? time for the fan. when a fan is being started from a stationary st ate, the pwm output is held at 100% duty cycle for the time specified in the table below before scaling to a lower speed. spin up time spin[2:0] 0 ms 000 100 ms 001 250 ms 010 400 ms 011 700 ms 100 1000 ms 101 2000 ms 110 4000 ms 111 table 16 fan spin-up register register 62, 63h: min/off, spike smoothing register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 62h r/w min/off, zone1 spike smoothing res res off res zn1e zn1-2 zn1-1 zn1-0 00 x 63h r/w zone2 spike smoothing zn2e zn2-2 zn2-1 zn2-0 res res res res 00 x the off/min bit 5 specifies whether the duty cycle will be 0% or minimum fan duty when the measured temperature falls below the temperature limi t register setting (see table 18 below). if the remote pins are connected to a processor or chipse t, instantaneous temperature spikes may be sampled by the ASC7512. fan speed algorithm has two phase s of filtering on temperat ure zone readings. first, a ?no-spike? value is created from the current temperature and th ree previous readings. this is an average of the two remaining values when the high and low values are removed. this is the te mperature used to determine pwm and is always running. the second phase is a user specified filt er and coefficient. this filter determines a smoothed temperature value, smooth t i , by taking the no-spike t i , subtracting the previous sm oothed temperature, smooth t i-1 , divided by 2^n and adding that to the previously smoothed temperat ure. n is a user selectable coefficient, in the range 1 to 8, designated zn1-2:zn1-0 for zone 1 and zn2-2:zn2-0 for zone 2. - 26 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 for the current temperature reading t i : no-spike t i = (discard min and max of (t i , t i-1 , t i-2 , t i-3 ))/2 smooth t i = (no-spike t i - smooth t i-1 )/2 n + smooth t i-1 if these spikes are not filtered, the cpu fan (if connected to ASC7512) may tu rn on prematurely or produce unpleasant noise. for this reason, any zone that is connected to a ch ipset or processor should have spike smoothing enabled. individual system characteristics will determine how large this coefficient should be. when spike smoothing is enabled, the temper ature reading registers will still reflect the current value of the temperature ? not the ?smoothed out? value. zn1e and zn2e enable temperature smoothing for zones 1 and 2 respectively. zn1-2, zn1-1 and zn1-0 control smoothing time for zone 1. zn2-2, zn2-1 and zn2-0 control smoothing time for zone 2. these registers become read-only when the ready/lock/start/ov erride register lock bit is set. any further attempts to write to these registers shall have no effect. 0 10 20 30 40 50 60 123456789101112 figure 10 representation of what temperature is passed to the ASC7512 auto fan control with (green) and without (red dashed) spike smoothing spike smoothing filter coefficient znn-[2:0] 8 000 7 001 6 010 5 011 4 100 3 101 2 110 1 111 table 17 spike smoothing pwm action off/min bit at 0% duty below limit 0 at min pwm duty below limit 1 table 18 pwm output below limit depending on value of off/min - 27 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 register 64h: minimum pwm duty cycle register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 64h r/w fan pwm minimum 7 6 5 4 3 2 1 0 80 x this register specifies the minimum duty cycle that t he pwm will output when the meas ured temperature reaches the temperature limit register setting. this register becomes read-only when the ready/lock/start/override register lock bi t is set. any further attempts to write to this register shall have no effect. after power up the default value is used whenever the ready/lock/start/override register start bit is cleared even though modi fications to this register are possible. register value minimum pwm % binary hex 0% 0000 0000 00 ~25% 0100 0000 40 ~50% (default) 1000 0000 80 ~75% 1100 0000 c0 100% 1111 1111 ff table 19 minimum pwm duty cycle setting register 67-68h: temperature limit register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 67h r/w zone1 fan temp limit 7 6 5 4 3 2 1 0 5a x 68h r/w zone2 fan temp limit 7 6 5 4 3 2 1 0 5a x these are the temperature limits for the individual zones. when the current te mperature equals this limit, the fan will be turned on if it is not already. when the temperature exceed s this limit, the fan speed will be increased according to the algorithm set forth in the auto fan range, pwm frequency register description, default = 90 c = 5ah this register becomes read-only when the ready/lock/start/override register lock bit is set. any further attempts to write to this register shall have no e ffect. after power up the default value is used whenever the ready/lock/start/override register start bit is cleared even though modifications to this register are possible. temperature fan temp limit (2?s complement) >127 c 0111 1111 +127 c 0111 1111 +125 c 0111 1101 +90 c (default) 0101 1010 +50 c 0011 0010 +25 c 0001 1001 0 c 0000 0000 -50 c 1100 1110 -127 c 1000 0001 table 20 fan temperature limit register - 8-bit two?s complement - 28 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 register 6a-6bh: temperature limit register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 6ah r/w zone 1 temp absolute limit 7 6 5 4 3 2 1 0 64 x 6bh r/w zone 2 temp absolute limit 7 6 5 4 3 2 1 0 64 x in the auto fan mode, if a zone exceeds the temperature set in the absolute temperature limit register, all of the pwm outputs will increase its duty cycle to 100%. th is is a safety feature that attempts to cool the system if there is a potentia lly catastrophic thermal ev ent. if set to 80h (-128 c), the feature is disabled. default = 100 c = 64h. these registers become read-only when the ready/lock/start/ov erride register lock bit is set. any further attempts to write to these registers shall have no effect. after power up the default values are us ed whenever the re ady/lock/start/override register start bit is cleared even though modi fications to these registers are possible. temperature absolute limit (2?s complement) >127 c 0111 1111 +127 c 0111 1111 +125 c 0111 1101 +100 c (default) 0110 0100 +50 c 0011 0010 +25 c 0001 1001 0 c 0000 0000 -50 c 1100 1110 -127 c 1000 0001 -128 c (disable) 1000 0000 table 21 absolute temperature limit register - 8-bit two?s complement register 6dh: thermal zone hysteresis register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 6dh r/w zone 1 and zone 2 hysteresis h1-3 h1-2 h1-1 h1-0 h2-3 h2-2 h2-1 h2-0 44 x if the temperature is above fan temp limit, then dr ops below fan temp limit, the following will occur: ? the fan will remain on, at fan pwm minimum, until the temperature goes a certain amount below fan temp limit. ? the hysteresis registers control this amount. see below table for details. this register becomes read-only when the ready/lock/start/override register lock bit is set. any further attempts to write to these registers shall have no effect. after power up the default value is used whenever the re ady/lock/start/override register start bit is cleared even though modi fications to this register are possible. temperature zone hysteresis hn-[3:0] 0 c 0000 1 c 0001 4 c (default) 0100 10 c 1010 15 c 1111 table 22 zone hysteresis register format - 29 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 register 75h: fan spin-up mode register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 75h r/w fan spin-up mode res res res res res res res pwm su 07 x the pwm su bit configures the pwm spin-up mode. if pwm su is cleared the spin-up time will terminate after time programmed by the fan configurat ion register has elapsed. when set to 1, the spin-up time will terminate early if the tach reading exceeds the tach minimum value or after the time programmed by the fan configur ation register has elapsed, which ever occurs first. this register becomes read-only when the ready/lock/start/override register lock bi t is set. any further attempts to write to this register shall have no effect. after power up the default value is used whenever the ready/lock/start/override register start bit is cleared even though modi fications to this register are possible. miscellaneous registers register 3eh, feh: company id register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3eh r company id 7 6 5 4 3 2 1 0 61 the company id register contains the company identification num ber. for andigilog this is 61h. this number is assigned by intel and is a method for uniquely identifying the part manufacturer . this register is read-only ? a write to this register ha s no effect. register 3fh: version/stepping register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3fh r version/stepping ver3 ver2 ver1 ver0 stp3 stp2 stp1 stp0 62 the four least significant bits of the ve rsion/stepping register [3:0] contain the cu rrent stepping of the as c7512 silicon. th e four most significant bits [7:4] reflect the ASC7512 base devic e number when set to a value of 0110b. for the ASC7512, this register will read 01101000b (62h). the register is used by application software to identify wh ich device in the hardware monitor family has been implemented in the given system. based on this information, software can determine which registers to read from and write to. further, application software may use the current stepping to implement work-around for bugs found in a specific silicon stepping. this register is read-only ? a writ e to this register has no effect. register 70-7fh: vendor specific registers these registers are for vendor specific feat ures, including test registers. they will not default to a specific value on power up. - 30 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 applications information remote diodes the ASC7512 is designed to work with a variety of remote sensors in the form of the substrate thermal diode of a cpu or graphics controller or a diode-connected transistor. actual diodes are not suited for these measurements. there is some variation in the performance of these diodes, described in terms of its departure from the ideal diode equation. this factor is called diode non- ideality, . nf the equation relating diode temperature to a change in thermal diode voltage with two driving currents is: v be = (nf ) kt q ln( n ) where: nf = diode non-ideality factor, (nominal 1.008). k = boltzman?s constant, (1.38 x 10 -23 ). t = diode junction temperature in kelvins. q = electron charge (1.6 x 10 -19 coulombs). n = ratio of the two driving currents (16). the ASC7512 is designed and trimmed for an expected nf value of 1.008, based on the typical value for the intel pentium? iii and amd athl on?. there is also a tolerance on the value provided. the values for other cpus and the 2n3904 may have different nominal values and tolerances. consult the cpu or gpu manufacturer?s data sheet for the nf factor. table 23 gives a representative sample of w hat one may expect in the range of non-ideality. the trend with cpus is for a lower value with a larger spread. when thermal diode has a non- ideality factor other than 1.008 the difference in temperature reading at a particular temperature may be interpreted with the following equation: ? ? ? ? ? ? ? ? = actual reported actual n t t 008 . 1 where: reported t = reported temperature in temperature register. actual t = actual remote diode temperature. actual n = selected diode?s non-ideality factor, nf . temperatures are in kelvins or c + 273.15. this equation assumes that the series resistance of the remote diode is the same fo r each. this resistance is given in the data sheet for the cpu and may vary from 2.5 ? to 4.5 ? . although the temperature error caused by non-ideality difference is directly proportional to the difference from 1.008, but a small difference in non-ideality results in a relatively large difference in temperature reading. for example, if there were a 1% tolerance in the non-ideality of a diode it would result in a 2.7 degree difference (at 0c) in the result (0.01 x 273.15). this difference varies with temperature such that a fixed offset value may only be used over a very narrow range. typical correction method required when measuring a wide range of temperature values is to scale the temperature reading in the host firmware. part nf min nf nom nf max series res pentium? iii (cpuid 68h) 1.0057 1.008 1.0125 pentium 4, 130nm 1.001 1.002 1.003 3.64 pentium 4, 90nm 1.011 3.33 intel pentium m 1.001 5 1.0022 1.0029 3.06 amd athlon? model 6 1.002 1.008 1.016 amd duron? models 7 and 8 1.002 1.008 1.016 amd athlon models 8 and 10 1.0000 1.0037 1.0090 2n3904 1.003 1.0046 1.005 table 23 representative cpu thermal diode and transistor non-ideality factors cpu or asic substrate remote diodes a substrate diode is a parasitic pnp transistor that has its collector tied to ground through the substrate and the base (d-) and emitter (d+) brought out to pins. connection to these pins is shown in figure 11. the non- ideality figures in table 23 include the effects of any package resistance and represent the value seen from the cpu socket. the temperature indicated will need to be compensated for the departure from a non-ideality of 1.008. d+ d- cpu ASC7512 substrate figure 11 cpu remote diode connection - 31 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 series resistance any external series resistance in the connections from the ASC7512 to the cpu pins should be accounted for in interpreting the results of a measurement. the impact of series resistance on the measured temperature is a result of measurement currents developing offset voltages t hat add to the diode voltage. this is relatively constant with temperature and may be corrected with a fixed value in the offset register. to determine the temperature im pact of resistance is as follows: t r = r s i d /t v or, t r = r s 90 a 230 v/ c = r s 0.391 c/ where: t r = difference in the temperat ure reading from actual. s r = total series resistance of interconnect (both leads). i d = difference in the two diode current levels (90a). v t = scale of temperature vs. v be (230v/c). for example, a total series resistance of 10 ? would give an offset of +3.9c. discrete remote diodes when sensing temperatures other than the cpu or gpu substrate, an npn or pnp transistor may be used. most commonly used are the 2n3904 and 2n3906. these have characteristics similar to the cpu substrate diode with non-ideality around 1.0046. they are connected with base to collector shorted as shown in figure 12. while it is important to minimize the distance to the remote diode to reduce high-frequency noise pickup, they may be located many feet away with proper shielding. shielded, twisted-pair cable is recommended, with the shield connected only at the ASC7512 end as close as possible to the ground pin of the device. as with the cpu substrat e diode, the temperature reported will be subject to the same errors due to non- ideality variation and series resistance. however, the transistor?s die temperature is usually not the temperature of interest and care must be taken to minimize the thermal resistance and physical distance between that temperature and the remote diode. the offset and response time will need to be characterized by the user. board layout considerations the distance between the remote sensor and the ASC7512 should be minimized. all wiring should be defended from high frequency noise sources and a balanced differential layout maintained on d+ and d-. any noise, both common-mode and differential, induced in the remote diode interconnect may result in an offset in the temperature reported. cir cuit board layout should follow the recommendation of figure 13. basically, use 10-mil lines and spaces with grounds on each side of the differential pair. choose the ground plane closest to the cpu when using the cpu?s remote diode. noise filtering is accomplished by using a bypass capacitor placed as close as possible to the ASC7512 d+ and d- pins. a 1.0nf ceramic capacitor is recommended, but up to 3.3nf may be used. additional filtering takes place within the ASC7512. it is recommended that the following guidelines be used to minimize noise and achieve highest accuracy: 1. place a 0.1f bypass capacitor to digital ground as close as possible to the power pin of the ASC7512. 2. match the trace routing of the d+ and d- leads and use a 1.0nf filter capacitor close to the ASC7512. use ground runs along side the pair to minimize differential coupling as in figure 13. 3. place the ASC7512 as close to the cpu or gpu remote diode leads as possible to minimize noise and series resistance. 4. avoid running diode connections close to or in parallel with high-speed busses, staying at least 2cm away. 5. avoid running diode connections close to on-board switching power supply inductors. 6. pc board leakage should be minimized by maintaining minimum trace spacing and covering traces over their full length with solder mask. 10 mils d + 10 mils d - gnd gnd d - 2n3906 d + ASC7512 d - 2n3904 d + ASC7512 figure 12 discrete remote diode connection figure 13 recommended remote diode circuit board interconnect - 32 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 thermal considerations the temperature of the asc7 512 will be close to that of the pc board on which it is mounted. conduction through the leads is the primary path for heat flow. the reported local sensor is very close to the circuit board temperature and typically between the board and ambient. in order to measure pc board temperature in an area of interest, such as the area around the cpu where voltage regulator components generate significant heat, a remote diode-connected transistor should be used. a surface- mount sot-23 or sot-223 is recommended. the small size is advantageous in minimizing response time because of its low thermal mass, but at the same time it has low surface area and a high thermal resistance to ambient air. a compromise must be achieved between minimizing thermal mass and increasing the surface area to lower the junction-to-ambient thermal resistance. in order to sense temperat ure of air-flows near board- mounted heat sources, such as memory modules, the sensor should be mounted ab ove the pc board. a to-92 packaged transistor is recommended. the power consumption of the ASC7512 is relatively low and should have little self-heating effect on the local sensor reading. at the hi ghest measurement rate the dissipation is less than 2mw, resulting in only a few tenths of a degree rise. evaluation board the asc7511/ASC7512evb provides a platform for evaluation of the operational characteristics of the asc7511 and ASC7512. the boar d features a graphical user interface (gui) to control and monitor all activities and readings of the asc7511. the provided software will run on a windows xp?-based desktop or laptop pc with a usb port. in addition to being a self-contained fan speed control demonstration, it may be connected into an operating pc?s fan and cpu diode to evaluate various settings under real operating conditions without the need to adjust bios code. after optimization, the settings may be programmed into the system. features: ? interactive gui for setting limits and operational configuration ? ASC7512 automatic fan control ? powered and operated from the usb port ? graphical readouts: ? temperature and alarms ? fan rpm ? automatic fan control state ? selectable on-board 2n3904 or wired remote diode ? headers for 2-, 3- and 4-wire fans ? customizable log file of readings ? saving of register setting configurations ? led indicator of pin state ? optional use of external 12v fan power for higher current fans ? optional connection to off-board smbus clients application diagrams the ASC7512 may be easily adapted to two-, three- or 4- wire fans for precise, wider-range fan speed control when compared to variable dc drive. pin 6 may optionally be used as alert , pulled up to 3.3v with a 10k resistor to warn the system of an extreme condition needing immediate attention in any fan configuration. figure 14 ASC7512 2-, 3- and 4-wire fan connections remote sensor remote sensor cpu ndt3055l or fdc637an smbdat smbclk 2.2k 2.2k 10k 5v 3.3v 5v 3-wire fan in cooling module ASC7512 vdd d + d - pwm gnd tach smbdat smbclk 6 8 7 5 3 1 2 4 remote sensor cpu smbdat smbclk 2.2k 2.2k 10k 5v 12v 4-wire fan in cooling module ASC7512 vdd d + d - pwm gnd tach smbdat smbclk 3 1 2 4 cpu ndt3055l or fdc637an smbdat smbclk 2.2k 2.2k 10k 5v 3.3v 5v 2-wire fan in cooling module ASC7512 vdd d + d - pwm gnd tach smbdat smbclk 6 8 7 5 3 1 2 4 6 8 7 5 10k 15k 7.5k 10k 3.3v 3.3v remote sensor remote sensor cpu ndt3055l or fdc637an smbdat smbclk 2.2k 2.2k 10k 5v 3.3v 5v 3-wire fan in cooling module ASC7512 vdd d + d - pwm gnd tach smbdat smbclk 6 8 7 5 6 8 7 5 3 1 2 4 3 1 2 4 remote sensor cpu smbdat smbclk 2.2k 2.2k 10k 5v 12v 4-wire fan in cooling module ASC7512 vdd d + d - pwm gnd tach smbdat smbclk 3 1 2 4 3 1 2 4 cpu ndt3055l or fdc637an smbdat smbclk 2.2k 2.2k 10k 5v 3.3v 5v 2-wire fan in cooling module ASC7512 vdd d + d - pwm gnd tach smbdat smbclk 6 8 7 5 6 8 7 5 3 1 2 4 6 8 7 5 6 8 7 5 10k 15k 7.5k 10k 10k 3.3v 3.3v optional alert - 33 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 physical dimensions in mil limeters unless otherwise noted: d8 package ? 8-lead sop package dimensions pb-free package 4.80mm (min) 4.98mm (max) 0.36mm (min) 0.46mm (max) 3.81mm (min) 3.99mm (max) 5.80mm (min) 6.20mm (max) 1.27mm bsc 1.52mm (min) 1.72mm (max) 0.53mm 0 (min) 8 (max) 0.25mm (min) 0.50mm (max) x 45 0.10mm (min) 0.25mm (max) 1.37mm (min) 1.57mm (max) 7 0.41mm (min) 1.27mm (max) detail a detail a 0.19mm (min) 0.25mm (max) - 34 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 m8 package ? 8-lead msop package dimensions pb-free package 2.85mm (min) 3.05mm (max) 4.75mm (min) 5.05mm (max) 0.95mm bsc 2.90mm (min) 3.10mm (max) 0.25mm (min) 0.40mm (max) 2.90mm (min) 3.10mm (max) 4.75mm (min) 5.05mm (max) 0.65mm bsc 1.10mm (max) 0.525mm bsc 0 (min) 6 (max) 2.85mm (min) 3.05mm (max) 0.10m m 0.78mm (min) 0.94mm (max) 0.05mm (min) 0.15mm (max) 2.90mm (min) 3.10mm (max) a a 0.25mm (min) 0.40mm (max) 0.25mm (min) 0.35mm (max) 0.13mm (min) 0.23mm (max) 0.13mm (min) 0.18mm (max) 0 (min) 6 (max) 9 (min) 15 (max) 0.40mm (min) 0.70mm (max) detail b section a detail b andigilog, inc. 8380 s. kyrene rd., suite 101 tempe, arizona 85284 tel: (480) 940-6200 fax: (480) 940-4255 - 35 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a05003 ASC7512 data sheet classifications preliminary specification this classification is shown on the heading of each page of a specification for produc ts that are either under development (design and qualification), or in the formative planning stages. andigilog reserves the right to change or discontinue these products without notice. new release specification this classification is shown on the heading of the first page only of a specification for products that are either under the later stages of development (characterization an d qualification), or in the early weeks of release to production. andigilog reserves the right to change the specification and information for these products without notice. fully released specification fully released datasheets do not contain any classifica tion in the first page header. these documents contain specification on products that are in full production. andigilog will not change any guaranteed limits without written notice to the customers. obsolete datasheets that were written prior to january 1, 2001 without any header classification information should be considered as ob solete and non-active specifications, or in the best case as preliminary specifications. pentium? is a trademark of intel corporation athlon? and duron? are trad emarks of amd corporation life support policy andigilog's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of andigilog, inc. as used herein: 1. life support devices or systems are dev ices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect it s safety or effectiveness. |
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